Parity Bit
Before studying the main topic, let’s discuss what do we mean by a parity bit. Well, it might be a 0 or 1 in data transmission, depending on the type of Parity checker or generator (even or odd).
Thus the bit that is added to the word containing the binary information for making the number of 1’s odd or even is said to be called as a Parity bit.
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Parity Generator and checker
The parity generator is a digital logic circuit that generates a parity bit in the transmitter. But when we talk about the Parity Checker, it’s a combinational circuit that checks the parity in the receiver.
The sum of the parity bit and data bit might be even or odd. In even parity, the total number of 1’s by adding both parity and data will be even. Whereas, when the odd parity is used the sum total of data and parity bit makes the total number of 1’s an odd value.
The fundamental principle in parity circuits is that the sum of even number of 1’s is always 1 and that of the odd number of 1’s is always 0. Such a circuit can easily be implemented by using the Ex-OR gate ( as it gives 0 when the number of inputs is even).
What is the parity generator?
It is a combinational circuit that takes n-bit of information (data) and generates an additional bit to be transmitted along with the n-bit data.
In the Even Parity scheme, if the number of 1’s is even in the data stream (info), then the parity bit is ‘0’ whereas when the total number of 1 count to be odd then ‘1’ is the parity bit.
In the Odd Parity scheme, if the number of 1’s is even in the data stream then ‘1’ is the parity bit but when the number of 1’s is odd then ‘0’ is used as the parity bit.
For an Even Parity scheme, the combinational circuit is shown below where 3-bit of data is accompanied with a parity bit (maybe 0/1 depending on the data stream).
Now let us understand both Even and Odd Parity Generator in a better way with the help of an example each.
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Even Parity Generator
Let us consider a 2-bit message to be transmitted with an even parity bit. Let the 2 inputs A & B are applied to the circuit and Y is the output bit parity. Now to generate the even parity bit Y, the total number of 1’s must be odd.
The below-shown is the truth table of Even Parity generator where the output (parity bit generator) becomes 1 when the number of inputs is odd else output remains 0.
| 2-Bit Message | Even Parity Bit Generator | |
| A | B | Y |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The K-map simplification for the 2-bit message even parity generator is
From the above table, the simplified expression of parity bit can be given as:
Y= A’ B + A B’
Y= A ⊕ B
The above expression could be implemented using an Ex-OR gate. The logic diagram is as shown. The 2-bit message along with the parity bit is transmitted to the receiving end where the checker circuit checks for the error.
Odd Parity Generator
Let us suppose 2-bit data is to be transmitted with an odd parity bit then the 2 inputs being A, B & Y will be the output (odd parity bit). The total number of 1’s must be even in order to get the odd parity bit.
In the below truth table, the parity bit ‘1’ is generated when the total number of 1’s is even in data bit (to make it odd).
| 2-bit message | Odd Parity bit Generator | |
| A | B | Y |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Using K-map, the above truth table can be simplified as below:
The expression for output parity bit Y can be given as:
Y = A’⊕ B (Ex-NOR )
This expression can be implemented by using one Ex-NOR gate. The 2-bit data along with the parity bit is transmitted to the receiver where parity checker checks for the error in the message.
Parity Checker
This circuit is used at the receiver where it checks for the possible errors in the message data. Also as Parity Generator, Parity Checker is of two types namely, Even Parity Checker and Odd Parity Checker.
Even Parity Checker
Let us suppose, the 2-bit input message along with the parity bit comes from the transmitter end. Thus 3-bits are applied as the input to the parity checker where it will check for the possible errors.
If the number of 1’s received at the receiver end is even then, the message received is error-free. But if the number of 1’s counts to be odd then the received message contains an error.
The truth table for Even Parity checker can be made as follows, Parity error checker Ee is 1 when the number of 1’s counts to be even, else it will be 0.
| 3-bit Message Received | Parity Error Check | ||
| A | B | Y | Ee |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
Odd Parity Checker
Now, let us assume the same scenario as above where the 2-bit input data along with the parity bit is transmitted through the transmitter. So in total, 3-bits are applied at the input of the Parity Checker.
Since the parity checker used here is an odd one, so the error will be decided on whether the number of 1’s is odd or not. If the number of 1’s at the receiving end counts to be even in number then an error has occurred. But if the number 1’s is odd then the transmission is taken as error-free.
The truth table for odd Parity Checker can be drawn as follows:
| 3-bit Message Received | Parity Error Check | ||
| A | B | Y | Eo |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
Parity Generator/Checker Advantages and Disadvantages
The advantage is its simplicity and ease of use. But along with these, there are few disadvantages also which are as follows:
- If there are errors in more than 1-bit then parity checker won’t be able to detect it.
- No way to find which bit is corrupted.
- Data correction is not possible, so data has to be retransmitted.
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103 thoughts on “Parity Generator and Parity Checker”
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I Want to design a circuit that takes a serial data stream from data in input. I want to get the high output if the data in the previous clocks have en even number of 1.
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i was working on parity generator verilog code, i found a problem while using nand gate at the output feedback terminal, it’s supposed to compliment/not the signal, but it seems not to be working.
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Yes, it can detect only single bit error, if more bits are corrupted then this fails.
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